My name is Per-Olof Bergstedt and I am a very experienced Digital IC Design Engineer with an additional knowledge of computers and internet.
My specialities are Verilog, VHDL, System Verilog, ASIC, FPGA, Digital Design, Digital Layout, Perl, Python, Linux, Unix, SoC, Embedded, Xilinx, Altera, Cadence, Synopsys.
I am now working for Synopsys. I have worked for BitSimNow, Samsung, ÅF, Zarlink Semiconductor, Ericsson and others.
I have an M.Sc EE from KTH Royal Institute of Technology in Stockholm. My name is on two patents. (US 7707329 and US 6091728 )
To contact me, send an e-mail to: